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ds094 (v3.2) march 8, 2007 www.xilinx.com 1 product specification ? 2002-2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 5.7 ns pin-to-pin delays - as low as 13 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis. refer to the coolrunner?-ii family data sheet for architecture description. - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 100-pin vqfp with 80 user i/o - 144-pin tqfp with 118 user i/o - 132-ball cp (0.5mm) bga with 106 user i/o - 208-pin pqfp with 173 user i/o - 256-ball ft (1.0mm) bga with 184 user i/o - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable (dge) signal control - two separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - pla architecture superior pinout retention 100% product term routability across function block - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pull-up on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels sstl2-1, sstl3-1, and hstl-1 i/o compatibility - hot pluggable description the coolrunner?-ii 256-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of sixteen function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. datagate is a method to selectively disable inputs of the cpld that are not of interest during certain points in time. 0 xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 00 product specification r
xc2c256 coolrunner-ii cpld 2 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. two i/o banks are available on the coolrunner-ii 256 macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii 256 macrocell cpld is i/o compatible with various i/o standards (see ta b l e 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high-performance and low power operation. supported i/o standards the coolrunner-ii 256 macrocell features lvcmos, lvttl, sstl and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvttl i/o standard is a gen- eral purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. both hstl and sstl i/o standards make use of a v ref pin for jedec compliance. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs table 1: i/o standards for xc2c256 (1) iostandard attribute output v ccio input v ccio input v ref board termination voltage v tt lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 (2) 1.5 1.5 n/a n/a hstl_1 1.5 1.5 0.75 0.75 sstl2_1 2.5 2.5 1.25 1.25 sstl3_1 3.3 3.3 1.5 1.5 (1)for information on vref, see xapp399 . (2) lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 30 50 70 100 120 150 170 190 220 240 typical i cc (ma) 0.021 11.68 19.40 27.01 38.18 45.54 56.32 63.37 70.40 80.90 88.03 notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). frequency (mhz) i cc (ma) 0 0 25 50 75 100 25 0 200 150 100 50
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 33 150 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 54 300 a i cc dynamic current f = 1 mhz - 410 a f = 50 mhz - 27 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?1 a notes: 1. 16-bit up/down, resettable binary counter (one counter per function block) tested at v cc = v ccio = 1.9v 2. see quality and reliability section of the coolrunner-ii family data sheet
xc2c256 coolrunner-ii cpld 4 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.8v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage - 3.0 3.6 v v ih high level input voltage - 2 3.9 v v il low level input voltage - ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 2.3 2.7 v v ih high level input voltage - 1.7 v ccio + 0.3 (1) v v il low level input voltage - ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.7 1.9 v v ih high level input voltage - 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage - ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 1.6 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 5 product specification r schmitt trigger input dc voltage specifications sstl2-1 dc voltage specifications v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 3.9 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v symbol parameter test conditions min. typ max. units v ccio input source voltage - 2.3 2.5 2.7 v v ref (1) input reference voltage - 1.15 1.25 1.35 v v tt (2) termination voltage - v ref ? 0.04 1.25 v ref + 0.04 v v ih high level input voltage - v ref + 0.18 - 3.9 v v il low level input voltage - ?0.3 - v ref ? 0.18 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.62 - - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - - 0.54 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices symbol parameter test conditions min. max. units
xc2c256 coolrunner-ii cpld 6 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r sstl3-1 dc voltage specifications hstl1 dc voltage specifications ac electrical characteristics over recommended operating conditions symbol parameter test conditions min. typ max. units v ccio input source voltage - 3.0 3.3 3.6 v v ref (1) input reference voltage - 1.3 1.5 1.7 v v tt (2) termination voltage - v ref ? 0.05 1.5 v ref + 0.05 v v ih high level input voltage - v ref + 0.2 - v ccio + 0.3 v v il low level input voltage - ?0.3 - v ref ? 0.2 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 1.1 - - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - - 0.7 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices symbol parameter test conditions min. typ max. units v ccio input source voltage - 1.4 1.5 1.6 v v ref (1) input reference voltage - 0.68 0.75 0.90 v v tt (2) termination voltage - - v ccio x 0.5 - v v ih high level input voltage - v ref + 0.1 - 1.9 v v il low level input voltage - ?0.3 - v ref ? 0.1 v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.4 - - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - - 0.4 v notes: 1. v ref should track the variations in v ccio , also peak-to-peak ac noise on v ref may not exceed 2% v ref 2. v tt of transmitting device must track v ref of receiving devices symbol parameter -6 -7 units min. max. min. max. t pd1 propagation delay single p-term - 5.7 - 6.7 ns t pd2 propagation delay or array - 6.0 - 7.5 ns t sud direct input register clock setup time 2.6 - 3.0 - ns t su1 setup time (single p-term) 2.4 - 2.8 - ns t su2 setup time (or array) 2.7 - 3.3 - ns t hd direct input register hold time 0 - 0 - ns t h p-term hold time 0 - 0 - ns t co clock to output - 4.5 - 6.0 ns f toggle (1) internal toggle rate - 450 - 300 mhz f system1 (2) maximum system frequency - 256 - 152 mhz f system2 (2) maximum system frequency - 238 - 141 mhz f ext1 (3) maximum external frequency - 145 - 114 mhz f ext2 (3) maximum external frequency - 139 - 108 mhz t psud direct input register p-term clock setup time 1.3 - 1.7 - ns
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 7 product specification r t psu1 p-term clock setup time (single p-term) 1.2 - 1.5 - ns t psu2 p-term clock setup time (or array) 1.5 - 2.0 - ns t phd direct input register p-term clock hold time 1.1 - 1.2 - ns t ph p-term clock hold 1.0 - 1.0 - ns t pco p-term clock to output - 6.5 - 7.3 ns t oe /t od global oe to output enable/disable - 5.6 - 7.0 ns t poe /t pod p-term oe to output enable/disable - 7.3 - 8.0 ns t moe /t mod macrocell driven oe to output enable/disable - 7.4 - 9.9 ns t pao p-term set/reset to output valid - 7.5 - 8.1 ns t ao global set/reset to output valid - 5.7 - 7.6 ns t suec register clock enable setup time 2.8 - 3.1 - ns t hec register clock enable hold time 0 - 0 - ns t cw global clock pulse width high or low 1.1 - 1.6 - ns t pcw p-term pulse width high or low 6.0 - 7.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 6.0 - 7.5 - ns t dgsu set-up before datagate latch assertion 0 - 0 - ns t dgh hold to datagate latch assertion 4.0 - 6.0 - ns t dgr datagate recovery to new data - 8.2 - 9.0 ns t dgw datagate low pulse width 2.5 - 3.5 - ns t cdrsu cdrst setup time before falling edge gclk2 1.6 - 2.0 - ns t cdrh hold time cdrst after falling edge gclk2 0 - 0 - ns t config (4) configuration time - 150 - 150 s notes: 1. f toggle is the maximum clock frequency to which a t-flip flop can reliably toggle (see the coolrunner-ii family data sheet for more information). 2. f system1 (1/t cycle ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while f system2 is through the or array. 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array. 4. typical configuration current during t config is approximately 7.7 m a. symbol parameter -6 -7 units min. max. min. max.
xc2c256 coolrunner-ii cpld 8 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r ( internal timing parameters symbol parameter (2) -6 -7 units min. max. min. max. buffer delays t in input buffer delay - 2.4 - 2.6 ns t din direct data register input delay - 3.1 - 3.9 ns t gck global clock buffer delay - 1.8 - 2.7 ns t gsr global set/reset buffer delay - 2.0 - 3.5 ns t gts global 3-state buffer delay - 2.1 - 3.0 ns t out output buffer delay - 2.3 - 2.6 ns t en output buffer enable/disable delay - 3.5 - 4.0 ns p-term delays t ct control term delay - 1.1 - 1.4 ns t logi1 single p-term delay adder - 0.5 - 1.1 ns t logi2 multiple p-term delay adder - 0.3 - 0.5 ns macrocell delay t pdi input to output valid - 0.5 - 0.7 ns t sui setup before clock 1.3 - 1.8 - ns t hi hold after clock 0 - 0 - ns t ecsu enable clock setup time 0.8 - 1.8 - ns t echo enable clock hold time 0 - 0 - ns t coi clock to output valid - 0.4 - 0.7 ns t aoi set/reset to output valid - 1.4 - 1.5 ns t cdbl clock doubler delay - 0 - 0 ns feedback delays t f feedback delay - 1.7 - 3.0 ns t oem macrocell to global oe delay - 1.7 - 2.5 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 3.0 - 4.0 ns t out15 output adder - 0.8 - 1.0 ns t slew15 output slew rate adder - 4.0 - 5.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 2.0 - 3.0 ns t out18 output adder - 0 - 0 ns t slew output slew rate adder - 2.0 - 4.0 ns
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 9 product specification r switching characteristics ac test circuit i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.6 - 0.7 ns t hys25 hysteresis input adder - 1.5 - 3.0 ns t out25 output adder - 0.8 - 1.0 ns t slew25 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 0.7 ns t hys33 hysteresis input adder - 1.2 - 3.0 ns t out33 output adder - 1.2 - 1.6 ns t slew33 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays hstl, sstl sstl2-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.4 - 1.0 ns output adder to t out - -0.5 - 0.0 ns sstl3-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.4 - 1.0 ns output adder to t out - -0.5 - 0.0 ns hstl-1 input adder to t in , t din , t gck , t gsr ,t gts - 0.6 - 1.0 ns output adder to t out - 0 - 0ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (2) -6 -7 units min. max. min. max. figure 2: derating curve for t pd number of outputs switching 12 4 8 1 6 3.0 4.0 5.0 v cc = v ccio = 1.8v, t = 25 o c t pd2 (ns) 5.5 4.5 3.5 ds092_02_09230 2 figure 3: ac load circuit r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 c l includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs. r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35pf 35pf 35pf ds_act_08_14_02 test point
xc2c256 coolrunner-ii cpld 10 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r typical i/v output curves the i/v curve illustrates the nominal amount of current that an i/o can source/sink at different voltage levels. figure 4: typical i/v curve for xc2c256 vo (output volts) xc256_voio_all_02070 3 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v iol
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 11 product specification r 11 pin descriptions function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank 11---2b32 1 2 - - - 208 b4 2 1(gsr) 3 99 a3 143 206 c4 2 1 4 - - 142 205 a2 2 1 5 - - - 203 a3 2 1 6 97 b4 140 202 a4 2 17------ 18------ 19------ 110------ 111------ 1 12 96 - 139 201 b5 2 1 13 95 - 138 200 a5 2 1 14 94 a4 137 199 e8 2 1 15 - - - 198 b6 2 1 16 - c5 - 197 c7 2 2(gts2) 1 1 a1 2 3 d3 2 22---4c32 2(gts3) 3 2 b2 3 5 e3 2 24-b146b22 2(gts0) 5 3 c3 5 7 d4 2 26---8d22 27------ 28------ 29------ 210------ 211------ 2(gts1) 12 4 c2 6 9 e5 2 213-c1710b12 2 146d2912e42 2157-1014c12 216-d1--e22 3 1 - - 136 196 a6 2 3 2 - b5 135 195 d7 2 3 3 - - 134 194 b7 2 3 4 - a5 - 193 e9 2 3 5 93 - 133 192 a7 2 3 6 c6 191 d8 2 37------ 38------ 39------ 310------ 311------ 3 12 92 - - 189 b8 2 3 13 - b6 - 188 c8 2 3 14 91 a6 132 187 a8 2 3 15 - c7 - 186 e11 2 3 16 90 b7 131 185 e10 2 4 1 8e31115f22 4 2 9 - 12 16 f3 2 4 3 10 e2 13 17 g4 2 44-e11418g32 4 5 11 f3 15 19 f5 2 4 6 12 f2 16 20 g5 2 47------ 48------ 49------ 410------ 411------ 4 12 - f1 17 21 h2 2 41313g1-22h42 414--1823h32 415----h12 416---25h52 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank
xc2c256 coolrunner-ii cpld 12 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r 51-l3-49r11 5 2 - - 33 48 n4 1 53---47n21 5(gck1) 4 23 l2 32 46 m3 1 5 5 l1 31 45 p1 1 5(gck0) 6 22 k3 30 44 m2 1 57------ 58------ 59------ 510------ 511------ 5 12 - - - 43 l3 1 513---41n11 5 14 - - 2840l41 515---39m11 516-k1-38l51 61-m13450n31 6 (cdrst) 224m23551p21 63---54p41 6(gck2) 4 27 n2 38 55 p5 1 65---56r21 66---57t11 67------ 68------ 69------ 610------ 611------ 6(dge) 12 28 p2 39 58 t2 1 6 13 - m3 40 60 n5 1 6 1429n34161r41 6 15 - p3 42 62 m5 1 6 1630m44363r51 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank 71---37k41 72---36l21 73---35k31 74---34l11 7 5 19 j2 26 32 k5 1 7 6 18 j1 25 31 k2 1 77------ 78------ 79------ 710------ 7 1117h32430j41 7 1216h22329k11 7 1315h12228j31 7 1414g32127j21 715-g220-j51 716--19-j11 81-n44464r61 8 2 - - 45 65 n6 1 8 3 - - 46 66 r3 1 84---67m61 8 5 - - 48 69 t3 1 8632-4970p61 87------ 88------ 89------ 810------ 81133m55071t41 8 1234n55172p71 8 1335p55273t51 81436m6-74n71 81537n6-75r71 816---76m71 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 13 product specification r 9 1 78 c12 112 160 b13 2 9 2 79 b12 113 161 b14 2 9 3 - - - 162 c13 2 9 4 80 a12 114 163 a15 2 9 5 164 c12 2 9 6 81 c11 115 165 b12 2 97------ 98------ 99------ 910------ 9 11 - - - 166 d13 2 9 12 82 b11 116 167 a14 2 9 13 - - 117 168 e13 2 9 14 - a11 118 169 a13 2 9 15 - - 119 170 c11 2 9 16 - c10 - 171 a12 2 10 1 77 a13 111 159 a16 2 10 2 76 b13 110 158 b15 2 10 3 74 c13 107 155 c14 2 10 4 73 c14 106 154 g11 2 10 5 72 d12 105 153 b16 2 10 6 71 d13 104 152 d15 2 10 7 - - - - - - 10 8 - - - - - - 10 9 - - - - - - 10 10 - - - - - - 10 11 151 e14 2 10 12 70 d14 103 150 c16 2 10 13 - - - 149 f14 2 10 14 - e12 102 148 f13 2 10 15 - - - 147 e15 2 10 16 - e13 101 146 g13 2 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank 11 1 - b10 - - b11 2 11 2 - - 173 d11 2 11 3 - a10 - 174 a11 2 11 4 - - - 175 d10 2 11 5 - c9 120 - b10 2 11 6 - - 121 - e12 2 11 7 - - - - - - 11 8 - - - - - - 11 9 - - - - - - 11 10 - - - - - - 11 11 85 a8 124 178 f12 2 11 12 86 b8 125 179 b9 2 11 13 87 c8 126 180 c9 2 11 14 89 - 128 182 c10 2 11 15 - - 129 183 a9 2 11 16 - - 130 184 d9 2 12 1 - - - 145 f15 2 12 2 - - 100 144 g14 2 12 3 - - - 143 e16 2 12 4 - - - 142 h12 2 12 5 - f12 - 140 f16 2 12 6 - f13 - 139 h16 2 12 7 - - - - - - 12 8 - - - - - - 12 9 - - - - - - 12 10 - - - - - - 12 11 68 f14 98 138 g15 2 12 12 - g12 97 137 h13 2 12 13 67 g13 96 136 g16 2 12 14 66 - 95 135 h14 2 12 15 65 - 94 134 h15 2 12 16 - - - - j12 2 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank
xc2c256 coolrunner-ii cpld 14 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r 13 1 - n13 75 107 r15 1 13 2 53 n14 76 108 t16 1 13 3 - m12 77 109 n14 1 13 4 54 - - 110 r16 1 13 5 - m13 78 111 n15 1 13 6 55 - 79 112 m15 1 13 7 - - - - - - 13 8 - - - - - - 13 9 - - - - - - 13 10 - - - - - - 13 11 - - - - - - 13 12 - m14 80 113 m13 1 13 13 56 - 81 114 p16 1 13 14 - l12 82 115 n16 1 13 15 - - - 116 l14 1 13 16 - l13 - 117 m14 1 14 1 52 p14 74 106 p15 1 14 2 - - 71 103 p14 1 14 3 50 p12 70 102 p13 1 14 4 - m11 69 101 r13 1 14 5 49 n11 - 100 n13 1 14 6 - p11 68 - r14 1 14 7 - - - - - - 14 8 - - - - - - 14 9 - - - - - - 14 10 - - - - - - 14 11 - - - - - - 14 12 - - - 99 t15 1 14 13 - - 66 97 r12 1 14 14 46 p10 64 95 n11 1 14 15 44 - - - m11 1 14 16 - p9 61 91 n10 1 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank 15 1 - - - 118 l15 1 15 2 - l14 83 119 l13 1 15 3 - - - 120 m12 1 15 4 - - - 121 m16 1 15 5 - - - 122 k14 1 15 6 - - - 123 l16 1 15 7 - - - - - - 15 8 - - - - - - 15 9 - - - - - - 15 10 - - - - - - 15 11 58 k13 85 125 k15 1 15 12 59 k14 86 126 l12 1 15 13 60 j12 87 127 k16 1 15 14 61 j13 88 128 j14 1 15 15 63 h13 91 - j15 1 15 16 64 h12 92 131 j13 1 16 1 - - - 90 p10 1 16 2 - - - 89 r10 1 16 3 - m8 - 88 t10 1 16 4 - - - 87 r9 1 16 5 43 n8 60 86 n9 1 16 6 42 - 59 85 m8 1 16 7 - - - - - - 16 8 - - - - - - 16 9 - - - - - - 16 10 - - - - - - 16 11 41 p8 58 84 t8 1 16 12 40 m7 57 83 p8 1 16 13 39 n7 56 82 r8 1 16 14 - - - 80 t7 1 16 15 - - 54 78 n8 1 16 16 - p6 53 77 t6 1 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gts, gsr and gck pins can be used for general purpose i/o. pin descriptions (continued) function block macro- cell vq100 cp132 tq144 pq208 ft256 i/o bank
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 15 product specification r xc2c256 jtag, power/ground, no connect pins and total user i/o pin type vq100 cp132 tq144 pq208 ft256 tck 48 m10 67 98 p12 tdi 45 m9 63 94 r11 tdo 83 b9 122 176 a10 tms 47 n10 65 96 n12 v ccaux (jtag supply voltage) 5d3 8 11 f4 power internal (v cc ) 26, 57 p1, k12, a2 1, 37, 84 1, 53, 124 p3, k13, d12, d5 power bank 1 i/o (v ccio1 ) 20, 38, 51 j3, p7, g14, p13 27, 55, 73, 93 33, 59, 79, 92, 105, 132 j6, k6, l7, l8, j11, k11, l10, l9 power bank 2 i/o (v ccio2 ) 88, 98 a14, c4, a7 109, 127, 141 26, 133, 157, 172, 181, 204 f7, f8, g6, h6, f10, f9, h11 ground 21, 25, 31, 62, 69, 75, 84, 100 k2, n1, p4, n9, n12, j14, h14, e14, b14, a9, b3 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 f11, f6, g10, g7, g8, g9, h10, h7, h8, h9, j10, j7, j8, j9, k10, k7, k8, k9, l11, l6 no connects - - - - a1, c2, e6, d1, e1, g2, f1, g1, m4, t9, p9, m9, m10, t11, t12, t13, p11, t14, j16, k12, d16, g12, c15, d14, d6, c6, e7, c5 total user i/o 80 106 118 173 184
xc2c256 coolrunner-ii cpld 16 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r ordering information part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o commercia l (c) industrial (i) (1) xc2c256-6vq100c 0.5mm 43.1 10.9 very thin quad flat pack 14mm x 14mm 80 c xc2c256-7vq100c 0.5mm 43.1 10.9 very thin quad flat pack 14mm x 14mm 80 c xc2c256-6cp132c 0.5mm 65.0 15.0 chip scale package 8mm x 8mm 106 c xc2c256-7cp132c 0.5mm 65.0 15.0 chip scale package 8mm x 8mm 106 c xc2c256-6tq144c 0.5mm 37.2 7.2 thin quad flat pack 20mm x 20mm 118 c xc2c256-7tq144c 0.5mm 37.2 7.2 thin quad flat pack 20mm x 20mm 118 c xc2c256-6pq208c 0.5mm 36.9 9.7 plastic quad flat pack 28mm x 28mm 173 c xc2c256-7pq208c 0.5mm 36.9 9.7 plastic quad flat pack 28mm x 28mm 173 c xc2c256-6ft256c 1.0mm 34.6 6.1 fine pitch thin bga 17mm x 17mm 184 c xc2c256-7ft256c 1.0mm 34.6 6.1 fine pitch thin bga 17mm x 17mm 184 c xc2c256-6vqg100c 0.5mm 43.1 10.9 very thin quad flat pack; pb-free 14mm x 14mm 80 c xc2c256-7vqg100c 0.5mm 43.1 10.9 very thin quad flat pack; pb-free 14mm x 14mm 80 c xc2c256-6cpg132c 0.5mm 65.0 15.0 chip scale package; pb-free 8mm x 8mm 106 c xc2c256-7cpg132c 0.5mm 65.0 15.0 chip scale package; pb-free 8mm x 8mm 106 c xc2c256-6tqg144c 0.5mm 37.2 7.2 thin quad flat pack; pb-free 20mm x 20mm 118 c xc2c256-7tqg144c 0.5mm 37.2 7.2 thin quad flat pack; pb-free 20mm x 20mm 118 c xc2c256-6pqg208c 0.5mm 36.9 9.7 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c256-7pqg208c 0.5mm 36.9 9.7 plastic quad flat pack; pb-free 28mm x 28mm 173 c xc2c256-6ftg256c 1.0mm 34.6 6.1 fine pitch thin bga; pb-free 17mm x 17mm 184 c xc2c256-7ftg256c 1.0mm 34.6 6.1 fine pitch thin bga; pb-free 17mm x 17mm 184 c xc2c256-7vq100i 0.5mm 43.1 10.9 very thin quad flat pack 14mm x 14mm 80 i xc2c256-7cp132i 0.5mm 65.0 15.0 chip scale package 8mm x 8mm 106 i xc2c256-7tq144i 0.5mm 37.2 7.2 thin quad flat pack 20mm x 20mm 118 i xc2c256-7pq208i 0.5mm 36.9 9.7 plastic quad flat pack 28mm x 28mm 173 i xc2c256-7ft256i 1.0mm 34.6 6.1 fine pitch thin bga 17mm x 17mm 184 i
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 17 product specification r device part marking figure 5: sample package with part marking note: due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale packages by line are: ? line 1 = x (xilinx logo) then truncated part number ? line 2 = not related to device part number ? line 3 = not related to device part number 1. line 4 = package code, speed, operating temperature, three digits not related to device part number. package codes: c5 = cp132, c6 = cpg132. xc2c256-7vqg100i 0.5mm 43.1 10.9 very thin quad flat pack; pb-free 14mm x 14mm 80 i xc2c256-7cpg132i 0.5mm 65.0 15.0 chip scale package; pb-free 8mm x 8mm 106 i XC2C256-7TQG144I 0.5mm 37.2 7.2 thin quad flat pack; pb-free 20mm x 20mm 118 i xc2c256-7pqg208i 0.5mm 36.9 9.7 plastic quad flat pack; pb-free 28mm x 28mm 173 i xc2c256-7ftg256i 1.0mm 34.6 6.1 fine pitch thin bga; pb-free 17mm x 17mm 184 i notes: 1. c = commercial (t a = 0c to +70c); i = industrial (t a = ?40c to +85c). part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o commercia l (c) industrial (i) (1) standard example: xc2c128 device speed grade package type number of pins temperature range -6 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -6 temperature range xc2cxxx tq144 7c device type package speed operating range this line not related to device part number r part marking for non-chip scale package
xc2c256 coolrunner-ii cpld 18 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r figure 6: vq100 very thin quad flat pack vq100 top view gnd i/o (3) vccio 2 i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio 2 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o vcc i/o (2) i/o (5) i/o i/o gnd i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o i/o tdi i/o tms tck i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o vccio 1 i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio1 gnd i/o (2) i/o (2) i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enab le (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - data gate
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 19 product specification r figure 7: cp132 chip scale package cp132 bottom view p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) i/o i/o vaux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o(2) vcc i/o gnd i/o i/o i/o i/o i/o i/o(2) i/o(1) vccio2 i/o i/o i/o(3) i/o i/o i/o gnd i/o i/o i/o vccio2 vcc i/o i/o i/o i/o gnd i/o i/o i/o tdo i/o i/o i/o gnd i/o(1) i/o i/o i/o vccio2 i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o tdi tck i/o i/o i/o i/o(4) gnd i/o i/o i/o i/o i/o i/o i/o gnd tms i/o gnd i/o i/o(2) (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c256 coolrunner-ii cpld 20 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r figure 8: tq144 thin quad flat pack v cc i/o (1) i/o (1) i/o i/o (1) i/o (1) i/o v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o gnd i/o (2) i/o i/o (2) i/o i/o i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tq144 top view v cc i/o (2) i/o (5) i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o i/o gnd tdi i/o tms i/o tck i/o i/o i/o i/o gnd 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o v ccio1 i/o i/o gnd gnd i/o i/o i/o i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio1 gnd i/o (3) i/o v ccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio2 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio2 (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 21 product specification r figure 9: pq208 quad flat package vcc i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o i/o(1) i/o vaux i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o vccio2 i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o(2) i/o i/o(2) i/o i/o i/o i/o i/o(4) gnd pq208 top view vcc i/o i/o(2) i/o i/o i/o(5) vccio1 i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 gnd tdi i/o tms i/o tck i/o i/o i/o i/o i/o gnd (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio2 vccio1 i/o gnd gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o gnd i/o(3) i/o vccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o vccio2 i/o i/o i/o gnd tdo i/o i/o i/o vccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
xc2c256 coolrunner-ii cpld 22 www.xilinx.com ds094 (v3.2) march 8, 2007 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. figure 10: ft256 fine pitch thin bga ft256 bottom view a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 i/o tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(3) i/o i/o i/o i/o i/o i/o i/o nc nc i/o nc i/o nc nc i/o i/o(1) i/o nc vcc i/o i/o i/o i/o nc vcc i/o(1) i/o nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc nc i/o(1) i/o(1) i/o nc i/o i/o vccio2 vaux i/o i/o i/o gnd vccio2 vccio2 vccio2 gnd i/o i/o i/o nc i/o i/o gnd i/o i/o i/o nc i/o gnd gnd gnd vccio2 i/o i/o nc nc i/o i/o gnd i/o i/o i/o i/o vccio2 gnd gnd gnd vccio2 i/o i/o i/o i/o i/o nc gnd i/o i/o i/o i/o vccio1 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o gnd i/o vcc i/o nc vccio1 gnd gnd gnd vccio1 i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o gnd vccio1 vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o nc nc i/o i/o i/o i/o nc i/o i/o i/o i/o i/o(2) i/o(2) i/o i/o i/o i/o i/o i/o i/o tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o tck nc nc i/o i/o i/o i/o(2) vcc i/o(4) i/o i/o i/o i/o i/o i/o i/o i/o tdi i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc nc nc nc nc i/o i/o i/o i/o i/o i/o(5) i/o i/o (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c256 coolrunner-ii cpld ds094 (v3.2) march 8, 2007 www.xilinx.com 23 product specification r additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 05/09/02 1.0 initial xilinx release. 05/13/02 1.1 updated ac electrical characteristics and added new parameters. 10/31/02 1.2 corrected package user i/o, added voltage referenced dc tables. 03/17/03 2.0 added characterization numbers for product release and device part marking 04/02/03 2.1 updated t sol max from 260 to 220. changed i ccsb units from ma to a. 01/26/04 2.2 updated device part marking. updated links and tsol. 02/26/04 2.3 corrected theta jc value on xc2c256-7tq144. 08/03/04 2.4 pb-free documentation 08/19/04 2.5 changes to i ccsb maximum specifications in dc electrical characteristics table, on page 3. 10/01/04 2.6 add asynchronous preset/reset pulse width specification to ac electrical characteristics. 03/07/05 2.7 removed -5 speed grade. changes to table 1, i/o standards. 06/28/05 2.8 move to product specification. change to t in25 , t out25 , t in33 , and t out33 for -7 speed grade. 03/20/06 2.9 add warranty disclaimer. add note to pin description table that gts, gsr and gck pins can be used for general purpose i/o. 5/20/06 3.0 moved t config specification values from min column to max column, page 7. 02/15/07 3.1 corrections to timing parameters t aoi , t psud , t psu1 , t psu2 , t phd , t pco , t poe , t pao , t ao , t suec , t cw , t cdrsu , and f toggle for -6 speed grade. corrections to t psud , t cw , and t cdrsu for the -7 speed grade. values now match the software. there were no changes to silicon or characterization. change to v ih specification for 2.5v and 1.8v lvcmos. 03/08/07 3.2 fixed typo in note for v il for lvcmos18; removed note for v il for lvcmos33.

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